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C64 CIRCUIT THEORY

[I/O, ROM and expansion port schematic]
I/O and ROM Address Decoding and Expansion Port.
I/O Address Decoding Logic
U17 is a Programmable logic array (PLA). The output on pin 12 called I/o goes "low" when any of the I/O devices controlled by U15 are selected. The addresses are listed below for each device.
VIC IC $D000 - $D02E
SID IC $D400 - $D7FF
Color Ram $D800 - $DBFF
CIA 1 $DC00 - $DC0F
CIA 2 $DD00 - $DD0F
I/O 1 $DE00 - $DEFF
I/O 2 $D 0 - $DFFF
ROM Address Decoding.
Basic ROM resides at locations $A000 - $BFFF. The output F1 pin 17 of the PLA U17 goes "low" when the BASIC ROM is selected. The KERNAL ROM resides at locations $E000 - $FFFF. The output F2 pin 16 of the PLA U17 goes "low" when the KERNAL ROM is selected. The CHARACTER GENERATOR ROM resides at locations $D000 - $DFFF. The output F3 pin 15 of the PLA U17 goes "low" when the Character Generator ROM is selected.
The Expans n Port Connections.
The expansion port is an extension of the microprocessor address, data, and control bus. ROML decodes addresses $8000 - $9FFF, and ROMH decodes addresses $E000 - $FFFF. These are outputs from the PLA used to select the catridge inserted in the expansion port. I/O 1 input from U15 decodes addresses $DE00 - $DEFF. I/O 2 output from U15 decodes addresses $DF00 - $DFFF.
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This page has been created by Sami Rautiainen.
Last updated February 11, 1998.
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