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C64 CIRCUIT THEORY

[Serial interface and user port schematic]
The Serial Interface and User Port Circuits
The Serial Interface.
U2 is a Complex Interface Adapter (CIA). Parallel port s nals PA3-PA7 control the serial bus interface. PA3 is the Attention (ATN) output. This signal is inverted by U8 before being transmitted to a device on the bus. PA4 is the clock output. Data transmitted from the C64 to a device on the bus is synchronized by this clock signal. U8 inverts the output PA4. PA5 is the data output. U8 inverts this output also. Data transmitted from a device on the bus to the C64 is synchronized by a clock generated by the transmitting device. The Clock signal is input on P . Data transmitted from a device on the bus to the C64 is input on PA7. When a device on the bus wants to communicate with the C64, SQR IN goes "low" indicating service is requested.
The User Port
Parallel port B of U2 (PB0 - PB7) is made available on the user port. Parallel data transfers with external device are made very easily through this parallel port. SP2 and SP1 are bi-directional serial ports. CNT1 and CNT2 are bi-directional synchronizing clock signals for each serial bus. r> [Prev] [Next] [Contents] [Commodore] [New] [Home]
This page has been created by Sami Rautiainen.
Last updated February 11, 1998.
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