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COMMON I.C.'S
PIN ASSIGNMENTS AND LOGIC

743274S3274LS3274F32
QUAD 2-INPUT OR GATE

PIN ASSIGNMENT
 LOGIC DIAGRAM
TRUTH TABLE

INPUTS OUTPUT
A B Y
L
L
H
H		 L
H
L
H		 L
H
H
H

H = HIGH voltage level
L = LOW voltage level


747474S7474LS7474F74
DUAL D-TYPE FLIP-FLOP (POSITIVE EDGE TRIGGERED)

PIN ASSIGNMENT


LOGIC DIAGRAM
TRUTH TABLE

OPERATING MODE INPUTS OUTPUTS

SD
RD		 CP D Q
Q
Asyn. Set
Asyn. Reset (Clear)
Undetermined (a)
Load "1" (Set)
Load "0" (Reset) 		L
H
L
H
H
 H
L
L
H
H
 X
X
X


X
X
X
h
l
 H
L
H
H
L
 L
H
L
L
H

H = HIGH voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level steady state.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = don't care.
= LOW-to-HIGH clock transition.

NOTE
(a) Both outputs will be HIGH while both
SD		 and
RD		 are LOW.
But the output states are unpredictable if
SD		 and
RD		 go HIGH simultaneously.


7412374LS123
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR

PIN ASSIGNMENT


LOGIC DIAGRAM
TRUTH TABLE

INPUTS OUTPUTS

RD
A		 B Q
Q
L
X
X
H
H
 X
H
X
L

L
 X
X
L

H
H
 L
L
L


 H
H
H
H = HIGH voltage level
L = LOW voltage level
X = Don't care
= LOW-to-HIGH transition
= HIGH-to-LOW transition
= One HIGH-level pulse
= One LOW-level pulse